Pads are metal contacts usually at the perimeter of a device which are manufactured as part of the integrated circuit device and connected to selected internal wires. Metal wires or tape automated bonding lines are bonded to the pads to connect the integrated circuit device to external pins. Internal components of IC devices, such as transistors, metal lines, and vias, are increasingly becoming smaller. However, the size of the pads has not shrunk comparably to the sizes of these internal components. Thus many IC devices are pad limited, i.e. cannot become smaller in area irrespective of the shrinkage of internal components because the number and size of the pads require that the circuit be of a given size.
To minimize total chip area, pads are sometimes eliminated. If enough pads are eliminated, the device can be made smaller, but may have reduced functionality. Moreover, removing pads in a conventional field programmable gate array (FPGA) device is not a trivial task, and typically requires a new layout of the device, or even architectural changes. The physical layout dependence between pads and logic elements remains a significant impediment to technology migration (downward scaling of geometries) since pad sizes don't shrink in correspondence to logic cell sizes and line widths.
FPGAs provide routing interconnect lines for connecting logic elements to pads and for interconnecting logic elements. Thus, routing congestion occurs at the perimeter of the chip due to routing signals between pads and the logic elements as well as routing signals in the interior of the chip between logic elements.